Display monitors are often adapted to display characters using a number of different resolutions. Resolution refers to the number of pixels used within a given area to display an object or a character. A number of different standards are known. For example, the VGA standard requires a resolution of 640 pixels by 480 pixels.
FIG. 1 is a logic block diagram of a VGA controller 10, as known in the prior art. VGA controller 10 is shown as including a VGA core 14 that is coupled to shared host interface 12 and shared memory controller 16. As shown, shared host interface 12 and shared memory controller 16 are respectively coupled to a host bus interface and a memory interface. FIG. 2 is a logic block diagram of VGA core 14, as known in the prior art. VGA core 14 is shown as including a CRT controller 20, an attribute controller 24 and a VGA graphics controller 22 adapted to handle two-dimensional operations.
Referring to FIG. 1, VGA controller 10 often operates in one of two modes, namely an alphanumerical mode or a graphics mode. In the graphics mode, the display data is flat, therefore, the memory planes contain bit patterns for each pixel displayed on the screen. The color of each pixel is individually specified and supplied directly to the color look-up table and delivered to the monitor.
In the VGA alphanumerical mode, each character has an associated ASCII value, an attribute, a font, and an unused field. FIG. 3 shows the organization of memory bit planes associated with each character in the alphanumeric mode, as known in the prior art. The ASCII value associated with each character is typically represented by 8 bits ranging in value from, e.g., 00 Hex to FF Hex. For example, ASCII value for the alphabet “A” is represented by Hex value 20. Alphanumeric characters may be displayed in monochrome or a multitude of colors. The ASCII values are stored in plane 0 of the memory planes shown in FIG. 3.
In the monochrome alphanumerical mode, the characters may be represented, for example, in low or high intensity, or with underlines. In the color alphanumeric mode, one of a multitude of colors may be selected for the foreground as well as for the background. In addition, the characters in the color mode may be instructed to blink or be underlined. In either color or monochrome mode, a character attribute, which is typically represented in one byte, is stored in plane 1 of the memory planes shown in FIG. 3. The font associated with each character is stored in bit plane 2. Fields stored in bit plane 3 are not used in the standard VGA alphanumeric mode, but can be used to store proprietary information such as custom fonts, if necessary
Each addressable location of the memory accessed by shared memory controller 16 is typically configured to store 32 bits. The first 16 bits of each address store the ASCII and the attribute bits associated with the same character; the remaining 16 bits of each memory address store the font and the unused bits that may be associated with the same or a different character.
Assume that the character to be displayed next is “T”. To display this character, the memory address containing the ASCII and the attribute parameter values associated with character “T” is first accessed, resulting in retrieval of 32 bits, 16 bits of which represent the ASCII and the attribute values for character “T”. The remaining 16 bits are discarded. The ASCII and attribute values are subsequently used to compute the memory address that contains the font parameter value associated with character “T”. The computed memory address is subsequently accessed to retrieve the font value for character “T”. During the retrieval of the font parameter value for character “T”, ASCII, attribute and unused parameter values are also retrieved, and are discarded.
As is known to those skilled in the art, in the alphanumeric mode, 80 characters are typically displayed in each row, although there are 132-wide alphanumeric modes as well. Assume that the character font height corresponds to 8 scan lines, i.e., there are 8 scan lines per row. To display the characters, during a first memory access, the display data associated with the first 8 adjacent characters in the first scan line of the row are retrieved from memory planes 0-3. The font and unused bits of the retrieved data are discarded since they may not be associated with the first 8 adjacent characters in the row. The retrieved ASCII and attribute bits are subsequently used to compute the memory locations in which the fonts associated with the first 8 adjacent characters are stored. Next, using the computed memory locations, the first scan line of fonts associated with the first 8 adjacent characters are retrieved. The ASCII, attribute and unused bits that are also retrieved during the retrieval of the font bits, are discarded. This process is repeated 10 times until the ASCII, attribute and fonts bits for all of the 80 characters in the current scan line of the row are so retrieved.
Next, this process is repeated for each of the scan lines 2 though 8 of the current row. Therefore, for each of scan lines 2 though 8, the ASCII and attribute bits for each character are retrieved again to enable the retrieval of the font bits for the characters in that scan line. It is understood that the ASCII and attribute bits for each character is the same in all scan lines. With each memory access, either the font and unused bits is discarded, or the ASCII, attribute and the unused bits are discarded. Accordingly, because there are 80 characters displayed in each row in the VGA alphanumeric mode, a total of at least 20 memory accesses are made to retrieve the ASCII, attribute and font parameter values associated with the characters in each scan line of the row. Consequently, total of at least 160 memory accesses are made to retrieve the ASCII, attribute and font parameter values associated with the 80 characters in the 8 scan lines that form the row, thus to enable the display of these characters.
FIG. 4 is a flowchart 100 of steps carried out by a VGA controller to display data in the alphanumeric mode, as known in the prior art. At step 102, a counter is reset to zero to indicate that processing of characters in the first scan line of a row is to begin. At step 104, the ASCII and attribute bits for the characters in the first row are fetched (i.e., retrieved) from the memory. At step 106, the font addresses for the characters in the first line are computed. At step 108, the fonts associated with the characters in the first line are fetched from the memory. At step 110, the fetched fonts are transmitted to the scan out buffer. At step 112, a determination is made as to whether the end of the current scan line has been reached. If not, then transition is made to 104, where more ASCII and attribute pairs are fetched. If yes, then transition is made to 114. At step 114, the counter's count is incremented to point to the next scan line. At step 116 a determination is made as to whether the data in all the scan lines have been processed. If not, transition is made to step 104 to fetch the ASCII and attribute bits associated with the next scan line of the row. If at step 116 it is determined that the data in all the scan lines of a current row have been processed, a transition is made to step 118 where the start address for the next row of characters is computed. From here, transition is made to 102 so as to allow the scan lines associated with the next row of characters to be processed and displayed on the monitor.
As seen from the above descriptions, in the prior art systems, the repeated retrieval and discard of the same ASCII and attribute data results in performance inefficiencies. Moreover, in such systems, font bits for each character is retrieved one scan line at a time further resulting in performance degradations. Furthermore, the multiple memory accesses required to fetch the font bits may cause the overall memory latency to become unacceptably large, thus resulting in screen tear. To handle this latency, the memory controller is often disposed in the same integrated circuit as that which includes the VGA controller, thus enabling the guarantee of a minimum read latency in such systems. This allows the requirements of isochronous clients, such as a VGA controller, to be built into the design of the memory controller. However, prior art systems are not adapted to support the relatively large latency that comes about if the VGA controller and the shared memory controller are formed in two separate integrated circuits.